1 ? cmos analog multiplexers and switches; specifications and appl ication considerations introduction this article describes several important considerations for the use of cmos analog mu ltiplexers and switches. it includes selection criteria, pa rameter definitions, handling and design precautions and interfacing. which switch to switch to? intersil provides a complete line of cmos analog switches including replacements for most of the available cmos competition. all types fe ature rugged no-latch-up construction, uniform characteristics over the analog signal range, and excellent high frequency characteristics. the hl-200 and hl-201 replace the popular, low cost dg200 and dg201 type dual and quad switches. the hl-5042 through hi-5051 are low resistance types, offering one to four switches in virtually all combinations. these replace the ih504x seri es with significantly better performance, and with both 75 ? and 30 ? switches available in all configurations. these are also plug-in replacements for many of the dg180 and dg 190 series of fet hybrid switches, offering the advantage of monolithic construction, but with slightly longer switching times. the analog switches do not contain overvoltage protection on the analog inputs, although they will withstand inputs 2 or 4 volts greater than the supplies. external current limiting should be provided if higher overvoltages are anticipated, such as a resistor in series with the analog input of value: r(ohms) (v in - v supply ) x 50 where v in is the maximum expected input voltage. all digital inputs do have overvoltage/static charge protection. data sheet definitions a. absolute maximum ratings as with all integrated circuits, these are maximum conditions which may be applied to a device (one at a time) without resulting in permanent damage. the device may, or may not, operate satisfactorily under these conditions - conditions listed under ?electrical specif ications? are the only ones guaranteed for satisfactory operation. b. v s , analog signal range the input analog signal range over which reasonable accurate switching will take place. for supply voltages lower than nominal, v s will be equal to the voltage span between the supplies. note that other parameters such as r on and leakage currents are guaranteed over a smaller input range, and would tend to degrade towards the v s limits. all off switches can withstand +v s applied at an input while -v s is applied to the output (or vi ce-versa) without switch breakdown - this is not true for some other manufacturers? devices. c. r on , on resistance the effective series on-switch resistance measured from input to output under specified conditions. note that r on changes with temperature (hig hest at high temperature), supply voltage, and to a lesser degree, with signal voltage and current. d. i s(off) , l d(off) , l d(on) , leakage currents currents measured under condit ions illustrated on the data sheet. a guarantee in only worst case high temperature leakages is preferred, bec ause room temperature picoampere levels are virtually impossible to measure repeatably on available autom ated test equipment. even under laboratory conditions, fixture and test equipment stray leakages may frequently exceed the device leakage. leakages tend to double every 10 o c temperature rise, so it is reasonable to assume that the +25 o c figure is about 0.001 times the +125 o c measurement; however, in some cases there may be ohmic leakages, such as on the package surface, which would make the +25 o c reading higher than calculated. each of these leakage figures is the algebraic sum of all currents at the point being measured: to each power supply, to ground, and through the swit ches; so the current direction cannot be predicted. in maki ng an error analysis it should be assumed that all leakages are in the worst-case direction. in most systems, l d(on) has the most effect, creating a voltage offset across the closed switch equal to i d(on) x r on . e. v al , v ah , input thresholds the lower and upper limits for the digital address input voltage at which the switching action takes place. all other parameters will be valid if all ?0? addressed inputs are less than v al and all ?1? inputs are greater than v ah . logic compatibility will be discussed in detail later in this paper. f. i a , input leakage current current at a digital input, which may be in either direction. digital inputs are similar to cmos logic inputs; connection to mos gates is through resistor-diode protection networks. unlike some other devices there is no dc negative resistance region which could create an oscillating condition. g. t a , t on , t off , access time the logic delay time plus output rise time to the 90% point of a full scale analog output swing. after this time the output will continue to rise, approaching the 100% point on an exponential curve determined by r on x c d(off) . application note august 2002 an520.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 h. t open , break-before-make delay the time delay between one switch turning off and another switch turning on, both switches being commanded simultaneously. this prevents a momentary condition of both switches being on, generally a very minor problem. i. c s(off) , c d(off) , c d(on) , input/output capacitance capacitance with respect to ground measured at the analog input/output terminals. c d(on) is generally the sum of c s(off) and c d(off) . c d(off) is usually the most important term as rise time /settling characteristics are determined by r on x c d(off) , as well as the high frequency transmission characteristics. j. c ds(off) , drain to source capacitance the equivalent capacitance shunting an open switch. k. off isolation the proportion of a high frequency signal applied to an open switch input appearing at the output: off isolation = 20 log v in v out this feedthrough is transmitted through c ds(off) to a load composed of c d(off) in parallel with the external load. the isolation generally decreases by 6db/octave with increasing frequency. l. c a , digital input capacitance capacitance to ground measured at digital input. this chiefly affects propagation delays when driven by cmos logic. m. p d , power dissipation: i+, i- quiescent power dissipation, p d = (v+ x i+) + (v- x i-). this may be specified both operating and standby (?enable? pin on/off). note that, as with al l cmos devices, dissipation increases with switching frequency, but that intersil devices exhibit much less of this effect. care and feeding of multiplexers and switches dielectrically isolated cmos ics require no more care in handling and use than any other semiconductor - bipolar or otherwise. however, they are not indestructible, and reasonable common sense care should be taken. in a laboratory breadboard, power should be shut off before inserting or removing any ic. it is especially important that supply lines have decoupling capacitors to ground permanently installed at the ic socket pins, as intermittent supply connections can create high voltage spikes through the inductance of a few feet of wire. because each of the major manufacturers of cmos multiplexers and switches uses a radically different process, it is urged that units from a ll prospective suppliers be equally tested in breadboards and prototypes. it will be interesting to note which types best survive the hazards of a few weeks of breadboard testing. particular care of semiconductors during incoming inspection and installation is quite important, because the cost of reworking finished assemblies with even a small percentage of preventable failures can seriously erode profits. all equipment should be periodically inspected for proper grounding. with these devices, it is not usually necessary to shackle personnel to the nearest water pipe, if reasonable attention is paid to clothing and floor coverings; but be alert for periods of unusually high static electricity. if special lines are already set up for handling mos devices, it wouldn?t hurt to use them. there are a few good rules for p.c. card layout: 1. each card or removable subassembly should contain de- coupling capacitors for each supply line to ground. this not only helps keep noise away from the analog lines, but gives good protection from st atic electricity damage when loose cards are handled. 2. when digital inputs come through a card connector, the pull-up resistor should be at the cmos input. this forces current through the connector and prevents possible dry circuit conditions (see following discussion on digital in- terface). 3. all unused digital inputs must be tied to logic ?0? (ground) or logic ?1? (logic supply or device + supply) depending on truth table and action desired. open inputs tend to oscil- late between ?0? and ?1?. good design practices also dic- tate using a series resistor ( 1k ?) when connecting an unused input to a supply other than gnd. it would also be best to ground any unused analog inputs/outputs and any uncommitted device pins. digital interface a. reference connection hl-5042 through hi-5051 and hi-1818a/1828a require connecting the v l pin to the digital logic supply (+5v to +15v). the hl-200/201/506a/507a have v ref pins which are normally left open when driving from +5 volt logic (dtl or ttl), but may be connected to higher logic supplies (to +15v) to raise the threshold levels when driving from cmos or hnll. the hi-200/201 will have significantly lower power dissipation when v ref is connected to a high level supply. the hi-506/507/508a/509a do not have v ref terminals, but will operate reliably with any logic supplied from +5 to +15 volts. b. dtl/ttl interface one major difference found in comparisons of similar devices from different manufacturers is the worst-case digital input high threshold (v ah or v ih ). these range anywhere from +2v to +5v; and anything greater than +2.4v is
3 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com obviously not compatible with worst-case ttl output levels. the fact is that no cmos input is truly ttl compatible unless an external pull-up re sistor is added. ttl output stages were not designed with cmos loads in mind. the experienced designer will always add a pull-up resistor from cmos input to the +5 volt supply when driving from ttl/dtl, for the following reasons: 1. interchangeability: allows substitution of similar devices from several manufacturers. 2. noise immunity: a ttl output in the ?high? condition can be quite high impedance. even when voltage noise im- munity seems satisfactory, the line is quite susceptible to induced noise. the pull-up re sistor will reduce the imped- ance while increasing voltage noise immunity. 3. compatibility: one manufactur er does guarantee +2.0 volt minimum v ah . however, this is accomplished with circuit- ry that is anything but ttl compatible: input current vs. voltage shows an abrupt positive then negative resis- tance region which is not the kind of load recommended for an emitter follower stage. a pull-up resistor will swamp out the negative resistance. other cmos inputs capaci- tively couple internal switching spikes to the input which could cause double-triggering without the pull-up resistor. 4. reliability: it shouldn?t happen with carefully processed ics, but any possible long te rm degradation of cmos de- vices usually involves threshold voltage shifts. the pull- up resistor will help maintain operation if input thresholds drift out of spec. on units without adequate input protec- tion, the resistor also helps protect the device when a loose p.c. card is handled. where the interface goes through a p.c. connector, the resistor will force current through the connector to break down any insulating film which otherwise might build up and cause erratic dry cir- cuit operation. a 2k ? resistor connected from the cmos input to the +5 volt supply is adequate fo r any ttl type output. if power consumption is critical, open collector ttl/dtl should be used, allowing a higher value resistor - the voltage drop across the resistor is computed from the sum of specified ?1? level leakage currents at the ttl output and cmos input. c. cmos interface the digital input circuitry on all devices is identical to series 4000 and 54c/74c logic inputs, and is compatible with cmos logic with supplies between +5v and +15v without external pull-up resistors. d. electromechanical interface when driving inputs from mechanical switches or relays, either a pull-up or pull-down resistor must be connected at the cmos input to clear the dry circuit film and to damp out any spikes, as illustrated in figure 1, (b) and (c). cmos cmos cmos (a) poor (b) good (c) good figure 1. pull-up/pull-down resistor connected at cmos input +v +v +v
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